Differential Pair Impedance Calculator

Estimate differential impedance for microstrip and stripline pairs using trace geometry, spacing, and dielectric inputs.

Differential Pair Impedance Calculator

Estimate differential pair impedance for high-speed PCB routing, then use the result as an early stackup and fabrication review reference.

Typically 4.2-4.6 for FR4

1oz Cu ≈ 0.035mm

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Microstrip

When to use this calculator

High-speed buses

Use it for USB, Ethernet, LVDS, PCIe, HDMI, and other differential routing where pair geometry strongly affects signal quality.

RF and signal-integrity review

Check whether your spacing and trace geometry are directionally close to the target pair impedance before final fabrication review.

Stackup discussion

Use it together with stackup planning and material review when discussing controlled differential routing with your PCB manufacturer.

Practical notes

• Differential impedance depends on both single-ended geometry and pair coupling.

• Spacing, dielectric thickness, copper thickness, and etching all affect the final result.

• Controlled differential pairs should always be finalized against the real fabrication stackup.

Frequently Asked Questions

What differential impedance target is most common?

100Ω differential is the most common target for many high-speed digital interfaces, but some interfaces and stackups use different values. Always confirm the target from your design rules and manufacturer requirements.

Why can the differential result change so much with spacing?

Because spacing changes electromagnetic coupling between the two traces. Tighter spacing increases coupling and changes the pair’s overall differential impedance.

Is this enough for production release?

No. Treat it as an engineering estimate. Final differential pair rules should be validated against the actual stackup, laminate data, and fabrication tolerances from your PCB manufacturer.

Need help turning a target differential pair into a manufacturable routing rule?

We can help review stackup assumptions, trace geometry, dielectric choices, and controlled impedance feasibility before fabrication.